160 search results - page 16 / 32 » Fast simulation of VLSI interconnects |
VLSID
2004
IEEE
15 years 11 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
TCAD
2002
14 years 11 months ago
2002
Interconnect optimization for VLSI circuits has received wide attention. To model routing surfaces, multiple circuit layers are freabstracted as a single rectilinear plane, ignori...
CCGRID
2001
IEEE
15 years 3 months ago
2001
IEEE
This paper describes the principles of an original adaptive interconnect for a computational cluster. Torus topology (2d or 3d) is used as a basis but nodes are allowed to effecti...
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GLVLSI
2009
IEEE
15 years 3 months ago
2009
IEEE
In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have ...
ISCA
2007
IEEE
15 years 5 months ago
2007
IEEE
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...