160 search results - page 18 / 32 » Fast simulation of VLSI interconnects |
DAC
2006
ACM
15 years 3 months ago
2006
ACM
Conventionally, signal net routing is almost always implemented as Steiner trees. However, non-tree topology is often superior on timing performance as well as tolerance to open f...
FCCM
2006
IEEE
15 years 5 months ago
2006
IEEE
— Dedicated, spatially configured FPGA interconnect is efficient for applications that require high throughput connections between processing elements (PEs) but with a limited ...
DATE
2008
IEEE
15 years 5 months ago
2008
IEEE
Statistical timing analysis needs a priori knowledge of process variations. Lack of such a priori knowledge of process variations prevents accurate statistical timing analysis, fo...
DAC
2006
ACM
16 years 8 days ago
2006
ACM
Steiner routing is a fundamental yet NP-hard problem in VLSI design and other research fields. In this paper, we propose to model the routing graph by an RC network with routing t...
EUROPAR
2009
Springer
15 years 5 months ago
2009
Springer
The size of supercomputers in numbers of processors is growing exponentially. Today’s largest supercomputers have upwards of a hundred thousand processors and tomorrow’s may ha...