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» Fast simulation of VLSI interconnects
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ASPDAC
2007
ACM
110views Hardware» more  ASPDAC 2007»
15 years 3 months ago
Fast Placement Optimization of Power Supply Pads
Power grid networks in VLSI circuits are required to provide adequate input supply to ensure reliable performance. In this paper, we propose algorithms to find the placement of pow...
Yu Zhong, Martin D. F. Wong
ISCAS
1994
IEEE
117views Hardware» more  ISCAS 1994»
15 years 3 months ago
Design of a Fast Sequential Decoding Algorithm Based on Dynamic Searching Strategy
This paper presents a new sequential decoding algorithm based on dynamic searching strategy to improve decoding efficiency. The searching strategy is to exploit both sorting and p...
Wen-Wei Yang, Li-Fu Jeng, Chen-Yi Lee
DATE
2003
IEEE
99views Hardware» more  DATE 2003»
15 years 4 months ago
Fast Computation of Data Correlation Using BDDs
Data correlation is a well-known problem that causes difficulty in VLSI testing. Based on a correlation metric, an efficient heuristic to select BIST registers has been proposed...
Zhihong Zeng, Qiushuang Zhang, Ian G. Harris, Maci...
INFOCOM
2005
IEEE
15 years 4 months ago
Fast replication in content distribution overlays
— We present SPIDER – a system for fast replication or distribution of large content from a single source to multiple sites interconnected over Internet or via a private networ...
Samrat Ganguly, Akhilesh Saxena, Sudeept Bhatnagar...
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
15 years 5 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...