160 search results - page 21 / 32 » Fast simulation of VLSI interconnects |
137
Voted
DAC
2012
ACM
13 years 6 months ago
2012
ACM
In this work, we propose a fast and accurate chip/package thermomechanical stress and reliability co-analysis tool for TSV-based 3D ICs. We also present a design optimization meth...
175
Voted
ISVLSI
2006
IEEE
15 years 9 months ago
2006
IEEE
Power consumption has been the primary issue in processor design, with various power reduction strategies being adopted from system-level to circuitlevel. In order to develop a po...
148
Voted
DAC
2005
ACM
15 years 5 months ago
2005
ACM
This paper proposes a fast decoupling capacitance (decap) allocation and budgeting algorithm for both early stage decap estimation and later stage decap minimization in today’s ...
172
Voted
GLVLSI
2009
IEEE
15 years 10 months ago
2009
IEEE
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
155
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GLVLSI
2008
IEEE
15 years 10 months ago
2008
IEEE
In this paper, we propose a novel statistical capacitance extraction method for interconnects considering process variations. The new method, called statCap, is based on the spect...