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» Fast simulation of VLSI interconnects
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ICPADS
2005
IEEE
15 years 4 months ago
Universal Routing in Distributed Networks
We show that universal routing can be achieved with low overhead in distributed networks. The validity of our results rests on a new network called the fat-stack. We show that fro...
Kevin F. Chen, Edwin Hsing-Mean Sha, Bin Xiao
ISCAS
1999
IEEE
106views Hardware» more  ISCAS 1999»
15 years 3 months ago
Repeater insertion in RLC lines for minimum propagation delay
- A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range o...
Yehea I. Ismail, Eby G. Friedman
ASPDAC
2009
ACM
137views Hardware» more  ASPDAC 2009»
15 years 3 months ago
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
-- Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next g...
Bao Liu
IJCAI
1997
15 years 19 days ago
Evolvable Hardware for Generalized Neural Networks
This paper describes an evolvable hardware (EHW) system for generalized neural network learning. We have developed an ASIC VLSI chip, which is a building block to configure a scal...
Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani...
PC
2007
112views Management» more  PC 2007»
14 years 10 months ago
Service address routing: a network-embedded resource management layer for cluster computing
Service address routing is introduced as a novel and powerful paradigm for the integration of resource management functions into the interconnection fabric of cluster computers. S...
Isaac D. Scherson, Daniel S. Valencia, Enrique Cau...