160 search results - page 26 / 32 » Fast simulation of VLSI interconnects |
VLSID
2000
IEEE
15 years 3 months ago
2000
IEEE
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
JOIN
2007
14 years 11 months ago
2007
In this paper, we show that universal routing can be achieved with low overhead in distributed networks. The validity of our results rests on a new network called the fat-stack. W...
ICCAD
2006
IEEE
15 years 8 months ago
2006
IEEE
Process variations in modern VLSI technologies are growing in both magnitude and dimensionality. To assess performance variability, complex simulation and performance models param...
139
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HIPEAC
2011
Springer
13 years 11 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
105
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MJ
2007
14 years 10 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...