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» Fast simulation of VLSI interconnects
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ISVLSI
2007
IEEE
150views VLSI» more  ISVLSI 2007»
15 years 10 months ago
Minimum-Congestion Placement for Y-interconnects: Some studies and observations
— Y -interconnects for VLSI chips are based on the use of global and semi-global wiring in only 0◦ , 60◦ , and 120◦ . Though X-interconnects are fast replacing the traditio...
Tuhina Samanta, Prasun Ghosal, Hafizur Rahaman, Pa...
GLVLSI
2006
IEEE
101views VLSI» more  GLVLSI 2006»
15 years 10 months ago
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance
Process variations have become a serious concern for nanometer technologies. The interconnect and device variations include interand intra-die variations of geometries, as well as...
Xiaoning Qi, Alex Gyure, Yansheng Luo, Sam C. Lo, ...
ISCAS
2008
IEEE
88views Hardware» more  ISCAS 2008»
15 years 10 months ago
A fast band matching technique for impedance extraction
— We present an efficient technique for the fast and accurate extraction of inductance of large-scale on-chip interconnects. Several simulation techniques exploit the sparsity o...
Jitesh Jain, Hong Li, Cheng-Kok Koh, Venkataramana...
TVLSI
2008
133views more  TVLSI 2008»
15 years 3 months ago
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fi...
Mitchell J. Myjak, José G. Delgado-Frias
TVLSI
2010
14 years 10 months ago
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling
To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp ...
Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He,...