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VLSID
2007
IEEE
92views VLSI» more  VLSID 2007»
15 years 10 months ago
Floorplanning in Modern FPGAs
State-of-the-art FPGA architectures have millions of gates in CLBs, Block RAMs, and Multiplier blocks which can host fairly large designs. While their physical design calls for oor...
Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu
CVIU
2010
115views more  CVIU 2010»
14 years 9 months ago
A modified model for the Lobula Giant Movement Detector and its FPGA implementation
Bio-inspired vision sensors are particularly appropriate candidates for navigation of vehicles or mobile robots due to their computational simplicity, allowing compact hardware im...
Hongying Meng, Kofi Appiah, Shigang Yue, Andrew Hu...
FPGA
2003
ACM
161views FPGA» more  FPGA 2003»
15 years 2 months ago
Implementation of BEE: a real-time large-scale hardware emulation engine
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
Chen Chang, Kimmo Kuusilinna, Brian C. Richards, R...
DATE
2005
IEEE
144views Hardware» more  DATE 2005»
15 years 3 months ago
An Accurate SER Estimation Method Based on Propagation Probability
In this paper, we present an accurate but very fast soft error rate (SER) estimation technique for digital circuits based on error propagation probability (EPP) computation. Exper...
Ghazanfar Asadi, Mehdi Baradaran Tahoori
ISCAS
2006
IEEE
102views Hardware» more  ISCAS 2006»
15 years 3 months ago
A fast dual-field modular arithmetic logic unit and its hardware implementation
— We propose a fast Modular Arithmetic Logic Unit (MALU) that is scalable in the digit size (d) and the field size (k). The datapath of MALU has chains of Carry Save Adders (CSA...
Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede