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85
Voted
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
15 years 7 months ago
Soft delay error analysis in logic circuits
— In this paper, we present an analysis methodology to compute circuit node sensitivity due to charged particle induced delay (timing) errors, Soft Delay Errors (SDE). We define...
Balkaran S. Gill, Christos A. Papachristou, Franci...
89
Voted
ICPP
1993
IEEE
15 years 5 months ago
Dependence Analysis and Architecture Design for Bit-Level Algorithms
:. In designing application-specific bit-level architectures and in programming existing bit-level processor arrays, it is necessary to expand a word-level algorithm into its bit-...
Weijia Shang, Benjamin W. Wah
110
Voted
ACL
2003
15 years 2 months ago
Fast Methods for Kernel-Based Text Analysis
Kernel-based learning (e.g., Support Vector Machines) has been successfully applied to many hard problems in Natural Language Processing (NLP). In NLP, although feature combinatio...
Taku Kudo, Yuji Matsumoto
96
Voted
CGO
2010
IEEE
15 years 7 months ago
Large program trace analysis and compression with ZDDs
Prior work has shown that reduced, ordered, binary decision diagrams (BDDs) can be a powerful tool for program trace analysis and visualization. Unfortunately, it can take hours o...
Graham D. Price, Manish Vachharajani
DATE
2007
IEEE
154views Hardware» more  DATE 2007»
15 years 7 months ago
Soft error rate analysis for sequential circuits
Due to reduction in device feature size and supply voltage, the sensitivity to radiation induced transient faults (soft errors) of digital systems increases dramatically. Intensiv...
Natasa Miskov-Zivanov, Diana Marculescu