Optimizations performed at link time or directly applied to final program executables have received increased attention in recent years. Such low-level optimizations can benefit...
While lower supply voltage is effective for energy reduction, it suffers performance loss. To mitigate the loss, we propose to execute only the part, which does not have any influ...
With the current trend toward multicore architectures, improved execution performance can no longer be obtained via traditional single-thread instruction level parallelism (ILP), ...
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
As processors continue to exploit more instruction level parallelism, a greater demand is placed on reducing the e ects of memory access latency. In this paper, we introduce a nov...