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» Fault Detection Likelihood of Test Sequence Length
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69
Voted
DFT
2003
IEEE
79views VLSI» more  DFT 2003»
15 years 3 months ago
Hybrid BIST Using an Incrementally Guided LFSR
A new hybrid BIST scheme is proposed which is based on using an “incrementally guided LFSR.” It very efficiently combines external deterministic data from the tester with on-c...
C. V. Krishna, Nur A. Touba
DSD
2005
IEEE
106views Hardware» more  DSD 2005»
15 years 4 months ago
Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment
1 This paper presents a method for power-constrained system-on-chip test scheduling in an abort-on-first-fail environment where the test is terminated as soon as a fault is detecte...
Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles
DDECS
2007
IEEE
90views Hardware» more  DDECS 2007»
15 years 2 months ago
Test Pattern Generator for Delay Faults
A method of generating test pairs for the delay faults is presented in this paper. The modification of the MISR register gives the source of test pairs. The modification of this r...
Tomasz Rudnicki, Andrzej Hlawiczka
75
Voted
ICFP
2006
ACM
15 years 10 months ago
Static typing for a faulty lambda calculus
A transient hardware fault occurs when an energetic particle strikes a transistor, causing it to change state. These faults do not cause permanent damage, but may result in incorr...
David Walker, Lester W. Mackey, Jay Ligatti, Georg...
TCAD
2008
114views more  TCAD 2008»
14 years 10 months ago
Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
At-speed functional testing, delay testing, and n-detection test sets are being used today to detect deep submicrometer defects. However, the resulting test data volumes are too hi...
Zhanglei Wang, Krishnendu Chakrabarty