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ISCA
2010
IEEE
219views Hardware» more  ISCA 2010»
15 years 2 months ago
Using hardware vulnerability factors to enhance AVF analysis
Fault tolerance is now a primary design constraint for all major microprocessors. One step in determining a processor’s compliance to its failure rate target is measuring the Ar...
Vilas Sridharan, David R. Kaeli
PRDC
2008
IEEE
15 years 4 months ago
Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy
Reliability has become a serious concern as systems embrace nanometer technologies. In this paper, we propose a novel approach for organizing redundancy that provides high degree ...
Viswanathan Subramanian, Arun K. Somani
SRDS
2007
IEEE
15 years 4 months ago
The Fail-Heterogeneous Architectural Model
Fault tolerant distributed protocols typically utilize a homogeneous fault model, either fail-crash or fail-Byzantine, where all processors are assumed to fail in the same manner....
Marco Serafini, Neeraj Suri
HOTDEP
2008
168views Hardware» more  HOTDEP 2008»
15 years 5 days ago
A Spin-Up Saved Is Energy Earned: Achieving Power-Efficient, Erasure-Coded Storage
Storage accounts for a significant amount of a data center's ever increasing power budget. As a consequence, energy consumption has joined performance and reliability as a do...
Kevin M. Greenan, Darrell D. E. Long, Ethan L. Mil...
ICDCS
2010
IEEE
15 years 1 months ago
Practical Robust Communication in DHTs Tolerating a Byzantine Adversary
—There are several analytical results on distributed hash tables (DHTs) that can tolerate Byzantine faults. Unfortunately, in such systems, operations such as data retrieval and ...
Maxwell Young, Aniket Kate, Ian Goldberg, Martin K...