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MIDDLEWARE
2009
Springer
15 years 4 months ago
Why Do Upgrades Fail and What Can We Do about It?
Abstract. Enterprise-system upgrades are unreliable and often produce downtime or data-loss. Errors in the upgrade procedure, such as broken dependencies, constitute the leading ca...
Tudor Dumitras, Priya Narasimhan
ISCA
1999
IEEE
187views Hardware» more  ISCA 1999»
15 years 2 months ago
Area Efficient Architectures for Information Integrity in Cache Memories
Information integrity in cache memories is a fundamental requirement for dependable computing. Conventional architectures for enhancing cache reliability using check codes make it...
Seongwoo Kim, Arun K. Somani
WISES
2004
14 years 11 months ago
Embedded Real-Time-Tracer - An Approach with IDE
-- Debugging software that runs on highly integrated System-on-Chip devices is complicated because conventional debug tools (like traditional In-Circuit Emulators and Logic Analyze...
Babak Rahbaran, Matthias Függer, Andreas Stei...
FDTC
2006
Springer
102views Cryptology» more  FDTC 2006»
15 years 1 months ago
Non-linear Residue Codes for Robust Public-Key Arithmetic
We present a scheme for robust multi-precision arithmetic over the positive integers, protected by a novel family of non-linear arithmetic residue codes. These codes have a very hi...
Gunnar Gaubatz, Berk Sunar, Mark G. Karpovsky
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
15 years 4 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...