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» Fault Tolerant External Memory Algorithms
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ICCAD
2005
IEEE
130views Hardware» more  ICCAD 2005»
15 years 6 months ago
A cache-defect-aware code placement algorithm for improving the performance of processors
— Yield improvement through exploiting fault-free sections of defective chips is a well-known technique [1][2]. The idea is to partition the circuitry of a chip in a way that fau...
Tohru Ishihara, Farzan Fallah
EUSFLAT
2009
233views Fuzzy Logic» more  EUSFLAT 2009»
14 years 7 months ago
SaM: A Split and Merge Algorithm for Fuzzy Frequent Item Set Mining
This paper presents SaM, a split and merge algorithm for frequent item set mining. Its distinguishing qualities are an exceptionally simple algorithm and data structure, which not ...
Christian Borgelt, Xiaomeng Wang
DAC
2009
ACM
15 years 10 months ago
Energy-aware error control coding for Flash memories
The use of Flash memories in portable embedded systems is ever increasing. This is because of the multi-level storage capability that makes them excellent candidates for high dens...
Veera Papirla, Chaitali Chakrabarti
HPDC
2009
IEEE
15 years 4 months ago
Interconnect agnostic checkpoint/restart in open MPI
Long running High Performance Computing (HPC) applications at scale must be able to tolerate inevitable faults if they are to harness current and future HPC systems. Message Passi...
Joshua Hursey, Timothy Mattox, Andrew Lumsdaine
DAC
2003
ACM
15 years 10 months ago
Seed encoding with LFSRs and cellular automata
Reseeding is used to improve fault coverage of pseudorandom testing. The seed corresponds to the initial state of the PRPG before filling the scan chain. In this paper, we present...
Ahmad A. Al-Yamani, Edward J. McCluskey