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PTS
1993
106views Hardware» more  PTS 1993»
15 years 1 months ago
Generating Synchronizable Test Sequences Based on Finite State Machine with Distributed Ports
In the area of testing communication systems, the interfaces between systems to be tested and their testers have great impact on test generation and fault detectability. Several t...
Gang Luo, Rachida Dssouli, Gregor von Bochmann, Pa...
90
Voted
RTAS
2005
IEEE
15 years 5 months ago
Out-of-Norm Assertions
Abstract— The increasing use of electronics in transport systems, such as the automotive and avionic domain, has lead to dramatic improvements with respect to functionality, safe...
Philipp Peti, Roman Obermaisser, Hermann Kopetz
ATS
1998
IEEE
170views Hardware» more  ATS 1998»
15 years 4 months ago
A Ring Architecture Strategy for BIST Test Pattern Generation
This paper presents a new effective Built-In Self Test (BIST) scheme that achieves 100% fault coverage with low area overhead, and without any modification of the circuit under tes...
Christophe Fagot, Olivier Gascuel, Patrick Girard,...
DFT
2007
IEEE
101views VLSI» more  DFT 2007»
15 years 6 months ago
Power Attacks Resistance of Cryptographic S-Boxes with Added Error Detection Circuits
Many side-channel attacks on implementations of cryptographic algorithms have been developed in recent years demonstrating the ease of extracting the secret key. In response, vari...
Francesco Regazzoni, Thomas Eisenbarth, Johann Gro...
ISSRE
2006
IEEE
15 years 5 months ago
Web Application Testing with Customized Test Requirements - An Experimental Comparison Study
Test suite reduction uses test requirement coverage to determine if the reduced test suite maintains the original suite’s requirement coverage. Based on observations from our pr...
Sreedevi Sampath, Sara Sprenkle, Emily Gibson, Lor...