Sciweavers

153 search results - page 3 / 31
» Fault origin adjudication
Sort
View
BCS
2008
14 years 11 months ago
Hardware Dependability in the Presence of Soft Errors
Using formal verification for designing hardware designs free from logic design bugs has been an active area of research since the last 15 years. Technology has matured and we hav...
Ashish Darbari, Bashir M. Al-Hashimi
IJHPCA
2006
117views more  IJHPCA 2006»
14 years 9 months ago
MPICH-V Project: A Multiprotocol Automatic Fault-Tolerant MPI
Abstract-- High performance computing platforms like Clusters, Grid and Desktop Grids are becoming larger and subject to more frequent failures. MPI is one of the most used message...
Aurelien Bouteiller, Thomas Hérault, G&eacu...
ATS
2002
IEEE
94views Hardware» more  ATS 2002»
15 years 2 months ago
Non-Intrusive Design of Concurrently Self-Testable FSMs
We propose a methodology for non-intrusive design of concurrently self-testable FSMs. Unlike duplication schemes, wherein a replica of the original FSM acts as a predictor-compara...
Petros Drineas, Yiorgos Makris
IPPS
2005
IEEE
15 years 3 months ago
A Maintenance-Oriented Fault Model for the DECOS Integrated Diagnostic Architecture
Abstract— The increasing use of electronics in the automotive and avionic domain has lead to dramatic improvements with respect to functionality, safety, and cost. However, with ...
Philipp Peti, Roman Obermaisser, Astrit Ademaj, He...
DFT
2003
IEEE
117views VLSI» more  DFT 2003»
15 years 2 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris