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» Fault tolerance in cellular automata at high fault rates
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DSD
2007
IEEE
132views Hardware» more  DSD 2007»
15 years 1 months ago
On-Chip Cache Device Scaling Limits and Effective Fault Repair Techniques in Future Nanoscale Technology
In this study, we investigate different cache fault tolerance techniques to determine which will be most effective when on-chip memory cell defect probabilities exceed those of cu...
David Roberts, Nam Sung Kim, Trevor N. Mudge
DAC
2009
ACM
15 years 2 months ago
Vicis: a reliable network for unreliable silicon
Process scaling has given designers billions of transistors to work with. As feature sizes near the atomic scale, extensive variation and wearout inevitably make margining unecono...
David Fick, Andrew DeOrio, Jin Hu, Valeria Bertacc...
EH
2005
IEEE
127views Hardware» more  EH 2005»
15 years 3 months ago
On the Robustness Achievable with Stochastic Development Processes
Manufacturing processes are a key source of faults in complex hardware systems. Minimizing this impact of manufacturing uncertainties is one way towards achieving fault tolerant s...
Shivakumar Viswanathan, Jordan B. Pollack
70
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FPL
2005
Springer
112views Hardware» more  FPL 2005»
15 years 3 months ago
Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement
Future process nodes have such small feature sizes that there will be an increase in the number of manufacturing defects per die. For large FPGAs, it will be critical to tolerate ...
Anthony J. Yu, Guy G. Lemieux
ICAI
2004
14 years 11 months ago
Integrating Robotic Sensor and Effector Capabilities with Multi-agent Organizations
Robots possess many effectors and sensors of various capability. It is often difficult, not only to integrate these numerous capabilities, but also to organize them to accomplish ...
Eric T. Matson, Scott A. DeLoach