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93
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CDES
2006
101views Hardware» more  CDES 2006»
15 years 1 months ago
Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors
- Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the latency and coverage. In this paper, a ne...
Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin
110
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INFOCOM
2008
IEEE
15 years 7 months ago
Towards Optimal Resource Allocation in Partial-Fault Tolerant Applications
—We introduce Zen, a new resource allocation framework that assigns application components to node clusters to achieve high availability for partial-fault tolerant (PFT) applicat...
Nikhil Bansal, Ranjita Bhagwan, Navendu Jain, Yoon...
130
Voted
FGCS
2010
119views more  FGCS 2010»
14 years 11 months ago
Characterizing fault tolerance in genetic programming
Evolutionary Algorithms, including Genetic Programming (GP), are frequently employed to solve difficult real-life problems, which can require up to days or months of computation. ...
Daniel Lombraña Gonzalez, Francisco Fern&aa...
108
Voted
APCSAC
2005
IEEE
15 years 6 months ago
A Fault-Tolerant Routing Strategy for Fibonacci-Class Cubes
Fibonacci Cubes (FCs), together with the enhanced and extended forms, are a family of interconnection topologies formed by diluting links from binary hypercube. While they scale up...
Zhang Xinhua, Peter Loh
NOCS
2010
IEEE
14 years 10 months ago
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Me...