Sciweavers

535 search results - page 91 / 107
» Fault tolerant high performance computing by a coding approa...
Sort
View
122
Voted
IEEEPACT
2006
IEEE
15 years 6 months ago
Self-checking instructions: reducing instruction redundancy for concurrent error detection
With reducing feature size, increasing chip capacity, and increasing clock speed, microprocessors are becoming increasingly susceptible to transient (soft) errors. Redundant multi...
Sumeet Kumar, Aneesh Aggarwal
97
Voted
IPPS
2008
IEEE
15 years 6 months ago
Lattice Boltzmann simulation optimization on leading multicore platforms
We present an auto-tuning approach to optimize application performance on emerging multicore architectures. The methodology extends the idea of searchbased performance optimizatio...
Samuel Williams, Jonathan Carter, Leonid Oliker, J...
141
Voted
HPCA
2011
IEEE
14 years 4 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
111
Voted
ICDCS
2005
IEEE
15 years 6 months ago
Resource-Aware Distributed Stream Management Using Dynamic Overlays
We consider distributed applications that continuously stream data across the network, where data needs to be aggregated and processed to produce a 'useful' stream of up...
Vibhore Kumar, Brian F. Cooper, Zhongtang Cai, Gre...
105
Voted
ESTIMEDIA
2009
Springer
14 years 10 months ago
Inter-kernel data reuse and pipelining on chip-multiprocessors for multimedia applications
The increasing demand for low power and high performance multimedia embedded systems has motivated the need for effective solutions to satisfy application bandwidth and latency req...
Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, ...