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» Fault tolerant mechanism design
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ISCA
2009
IEEE
136views Hardware» more  ISCA 2009»
15 years 8 months ago
Architectural core salvaging in a multi-core processor for hard-error tolerance
The incidence of hard errors in CPUs is a challenge for future multicore designs due to increasing total core area. Even if the location and nature of hard errors are known a prio...
Michael D. Powell, Arijit Biswas, Shantanu Gupta, ...
WCNC
2008
IEEE
15 years 8 months ago
On Collision-Tolerant Transmission with Directional Antennas
—The application of directional antennas in wireless networks brings numerous benefits, such as increased spatial reuse and mitigated interferences. Most MAC protocols with dire...
Hongning Dai, Kam-Wing Ng, Min-You Wu
MICRO
2008
IEEE
159views Hardware» more  MICRO 2008»
15 years 8 months ago
A novel cache architecture with enhanced performance and security
—Caches ideally should have low miss rates and short access times, and should be power efficient at the same time. Such design goals are often contradictory in practice. Recent f...
Zhenghong Wang, Ruby B. Lee
EMSOFT
2011
Springer
14 years 1 months ago
From boolean to quantitative synthesis
Motivated by improvements in constraint-solving technology and by the increase of routinely available computational power, partial-program synthesis is emerging as an effective a...
Pavol Cerný, Thomas A. Henzinger
ICPADS
2006
IEEE
15 years 7 months ago
Fast Convergence in Self-Stabilizing Wireless Networks
The advent of large scale multi-hop wireless networks highlights problems of fault tolerance and scale in distributed system, motivating designs that autonomously recover from tra...
Nathalie Mitton, Eric Fleury, Isabelle Guér...