936 search results - page 108 / 188 » Fault tolerant mechanism design |
GLVLSI
2006
IEEE
15 years 7 months ago
2006
IEEE
This paper presents a systematic design methodology for yield enhancement of asynchronous logic circuits using 3-D (3-Dimensional) integration technology. In this design, the targ...
147
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ISORC
2003
IEEE
15 years 7 months ago
2003
IEEE
Fault tolerance schemes for mobile agents to survive agent server crash failures are complex since developers normally have no control over remote agent servers. Some solutions mo...
116
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EUROSYS
2011
ACM
14 years 5 months ago
2011
ACM
Traditional agreement-based Byzantine fault-tolerant (BFT) systems process all requests on all replicas to ensure consistency. In addition to the overhead for BFT protocol and sta...
115
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ETS
2011
IEEE
14 years 1 months ago
2011
IEEE
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
ATS
2009
IEEE
15 years 8 months ago
2009
IEEE
Power distribution network (PDN) designs for today’s high performance integrated circuits (ICs) typically occupy a significant share of metal resources in the circuit, and henc...