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» Fault tolerant mechanism design
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ISCA
2007
IEEE
130views Hardware» more  ISCA 2007»
15 years 8 months ago
Dynamic prediction of architectural vulnerability from microarchitectural state
Transient faults due to particle strikes are a key challenge in microprocessor design. Driven by exponentially increasing transistor counts, per-chip faults are a growing burden. ...
Kristen R. Walcott, Greg Humphreys, Sudhanva Gurum...
124
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IEEECIT
2010
IEEE
15 years 6 days ago
CFCSS without Aliasing for SPARC Architecture
With the increasing popularity of COTS (commercial off the shelf) components and multi-core processor in space and aviation applications, software fault tolerance becomes attracti...
Chao Wang, Zhongchuan Fu, Hongsong Chen, Wei Ba, B...
DSN
2003
IEEE
15 years 7 months ago
Integrating Recovery Strategies into a Primary Substation Automation System
The DepAuDE architecture provides middleware to integrate fault tolerance support into distributed embedded automation applications. It allows error recovery to be expressed in te...
Geert Deconinck, Vincenzo De Florio, Ronnie Belman...
ISLPED
2005
ACM
136views Hardware» more  ISLPED 2005»
15 years 7 months ago
Energy efficient SEU-tolerance in DVS-enabled real-time systems through information redundancy
Concerns about the reliability of real-time embedded systems that employ dynamic voltage scaling has recently been highlighted [1,2,3], focusing on transient-fault-tolerance techn...
Alireza Ejlali, Marcus T. Schmitz, Bashir M. Al-Ha...
ICN
2001
Springer
15 years 6 months ago
An Evaluation of Shared Multicast Trees with Multiple Active Cores
Abstract. Core-based multicast trees use less router state, but have significant drawbacks when compared to shortest-path trees, namely higher delay and poor fault tolerance. We e...
Daniel Zappala, Aaron Fabbri