936 search results - page 132 / 188 » Fault tolerant mechanism design |
186
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ASPLOS
2009
ACM
16 years 15 days ago
2009
ACM
Future processors are expected to observe increasing rates of hardware faults. Using Dual-Modular Redundancy (DMR), two cores of a multicore can be loosely coupled to redundantly ...
ISCA
2010
IEEE
15 years 3 months ago
2010
IEEE
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
GLVLSI
2003
IEEE
15 years 5 months ago
2003
IEEE
In this paper a novel reseeding architecture for scan-based BIST, which uses an LFSR as TPG, is proposed. Multiple cells of the LFSR are utilized as sources for feeding the scan c...
ISQED
2002
IEEE
15 years 4 months ago
2002
IEEE
Critical systems like pace-makers, defibrillators, wearable computers and other electronic gadgets have to be designed not only for reliability but also for ultra-low power consu...
104
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CF
2009
ACM
14 years 9 months ago
2009
ACM
Emulation sits between simulation and experimentation to complete the set of tools available for software designers to evaluate their software and predict behavior under condition...