936 search results - page 42 / 188 » Fault tolerant mechanism design |
113
click to vote
DFT
2005
IEEE
15 years 5 months ago
2005
IEEE
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other...
DFT
2007
IEEE
15 years 6 months ago
2007
IEEE
This paper presents a new routing protocol of network-on-chip(Noc) called ‘Source Routing for Noc’(SRN) for fault tolerant communication of Systems-on-chip(Soc). The proposed ...
ICES
2003
Springer
15 years 5 months ago
2003
Springer
In this article, we introduce the approach to the realization of ontogenetic development and fault tolerance that will be implemented in the POEtic tissue, a novel reconfigurable ...
OSDI
2000
ACM
15 years 1 months ago
2000
ACM
This paper describes an asynchronous state-machine replication system that tolerates Byzantine faults, which can be caused by malicious attacks or software errors. Our system is t...
102
click to vote
DAC
2005
ACM
15 years 1 months ago
2005
ACM
1 This paper presents a transient faults sensitivity evaluation for Quasi Delay Insensitive (QDI) asynchronous circuits. Because of their specific architecture, asynchronous circui...