936 search results - page 86 / 188 » Fault tolerant mechanism design |
VLSID
2004
IEEE
16 years 8 days ago
2004
IEEE
As we move from deep submicron technology to nanotechnology for device manufacture, the need for defect-tolerant architectures is gaining importance. This is because, at the nanos...
EMSOFT
2007
Springer
15 years 6 months ago
2007
Springer
The design of safety-critical systems has typically adopted static techniques to simplify error detection and fault tolerance. However, economic pressure to reduce costs is exposi...
111
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ISLPED
2007
ACM
15 years 1 months ago
2007
ACM
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
GLVLSI
2007
IEEE
15 years 6 months ago
2007
IEEE
The path-delay fault simulation of functional tests on complex circuits such as current processor-based systems is a daunting task. The amount of computing power and memory needed...
115
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ICISC
2008
15 years 1 months ago
2008
We propose a number of techniques for securing finite state machines (FSMs) against fault injection attacks. The proposed security mechanisms are based on physically unclonable fun...