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» Fault tolerant mechanism design
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SAC
2005
ACM
15 years 7 months ago
Efficient placement and routing in grid-based networks
This paper presents an efficient technique for placement and routing of sensors/actuators and processing units in a grid network. Our system requires an extremely high level of ro...
Roozbeh Jafari, Foad Dabiri, Bo-Kyung Choi, Majid ...
ISCA
1998
IEEE
118views Hardware» more  ISCA 1998»
15 years 6 months ago
Active Messages: A Mechanism for Integrated Communication and Computation
The design challenge for large-scale multiprocessors is (1) to minimize communication overhead, (2) allow communication to overlap computation, and (3) coordinate the two without ...
Thorsten von Eicken, David E. Culler, Seth Copen G...
SOSP
2007
ACM
15 years 10 months ago
Attested append-only memory: making adversaries stick to their word
Researchers have made great strides in improving the fault tolerance of both centralized and replicated systems against arbitrary (Byzantine) faults. However, there are hard limit...
Byung-Gon Chun, Petros Maniatis, Scott Shenker, Jo...
VTS
2007
IEEE
129views Hardware» more  VTS 2007»
15 years 8 months ago
Supply Voltage Noise Aware ATPG for Transition Delay Faults
The sensitivity of very deep submicron designs to supply voltage noise is increasing due to higher path delay variations and reduced noise margins with supply noise scaling. The s...
Nisar Ahmed, Mohammad Tehranipoor, Vinay Jayaram
ISCA
2009
IEEE
159views Hardware» more  ISCA 2009»
15 years 8 months ago
End-to-end register data-flow continuous self-test
While Moore’s Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in t...
Javier Carretero, Pedro Chaparro, Xavier Vera, Jau...