936 search results - page 9 / 188 » Fault tolerant mechanism design |
92
Voted
NOCS
2010
IEEE
14 years 7 months ago
2010
IEEE
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
ISPA
2005
Springer
15 years 3 months ago
2005
Springer
Abstract. This paper proposes a novel scheme, named ER-TCP, which transparently masks the failures happened on the server nodes in a cluster from clients at TCP connection granular...
DSD
2010
IEEE
14 years 9 months ago
2010
IEEE
Abstract—Continuously shrinking feature sizes cause an increasing vulnerability of digital circuits. Manufacturing failures and transient faults may tamper the functionality. Aut...
ICRA
1994
IEEE
15 years 1 months ago
1994
IEEE
The application of robots in critical missions in hazardous environments requires the development of reliable or fault tolerant manipulators. In this paper, we define fault tolera...
CGO
2005
IEEE
15 years 3 months ago
2005
IEEE
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...