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NOCS
2007
IEEE
15 years 4 months ago
Implementing DSP Algorithms with On-Chip Networks
Many DSP algorithms are very computationally intensive. They are typically implemented using an ensemble of processing elements (PEs) operating in parallel. The results from PEs n...
Xiang Wu, Tamer Ragheb, Adnan Aziz, Yehia Massoud
SBACPAD
2005
IEEE
177views Hardware» more  SBACPAD 2005»
15 years 3 months ago
Automatic Data-Flow Graph Generation of MPI Programs
The Data-Flow Graph (DFG) of a parallel application is frequently used to take scheduling decisions, based on the information that it models (dependencies among the tasks and volu...
Rafael Ennes Silva, Guilherme P. Pezzi, Nicolas Ma...
FPL
2004
Springer
117views Hardware» more  FPL 2004»
15 years 3 months ago
Flow Monitoring in High-Speed Networks with 2D Hash Tables
Abstract. Flow monitoring is a required task for a variety of networking applications including fair scheduling and intrusion/anomaly detection. Existing flow monitoring techniques...
David Nguyen, Joseph Zambreno, Gokhan Memik
MICRO
1994
IEEE
81views Hardware» more  MICRO 1994»
15 years 2 months ago
Register file port requirements of transport triggered architectures
Exploitation of large amounts of instruction level parallelism requires a large amount of connectivity between the shared register file and the function units; this connectivity i...
Jan Hoogerbrugge, Henk Corporaal
IPPS
2003
IEEE
15 years 3 months ago
Homeostatic and Tendency-Based CPU Load Predictions
The dynamic nature of a resource-sharing environment means that applications must be able to adapt their behavior in response to changes in system status. Predictions of future sy...
Lingyun Yang, Ian T. Foster, Jennifer M. Schopf