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85
Voted
IPPS
2009
IEEE
15 years 10 months ago
2009
IEEE
127
click to vote
ICPP
1996
IEEE
15 years 8 months ago
1996
IEEE
Tiling exploits temporal reuse carried by an outer loop of a loop nest to enhance cache locality. Loop skewing is typically required to make tiling legal. This restricts parallelis...
147
Voted
ICPADS
2005
IEEE
15 years 9 months ago
2005
IEEE
Low energy consumptions are extremely important in real-time embedded systems, and scheduling is one of the techniques used to obtain lower energy consumptions. In this paper, we ...
132
Voted
SPAA
1995
ACM
15 years 7 months ago
1995
ACM
Many high-level parallel programming languages allow for fine-grained parallelism. As in the popular work-time framework for parallel algorithm design, programs written in such lan...
102
Voted
EUROPAR
2006
Springer
15 years 7 months ago
2006
Springer
This paper presents the integration of a multi-level scheduler in the YML architecture. It demonstrates the advantages of this architecture based on a component model and why it is...