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HPCA
2008
IEEE
15 years 10 months ago
Performance-aware speculation control using wrong path usefulness prediction
Fetch gating mechanisms have been proposed to gate the processor pipeline to reduce the wasted energy consumption due to wrongpath (i.e. mis-speculated) instructions. These scheme...
Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Pa...
HPCA
2008
IEEE
15 years 10 months ago
Runahead Threads to improve SMT performance
In this paper, we propose Runahead Threads (RaT) as a valuable solution for both reducing resource contention and exploiting memory-level parallelism in Simultaneous Multithreaded...
Tanausú Ramírez, Alex Pajuelo, Olive...
CASES
2007
ACM
15 years 1 months ago
A low power front-end for embedded processors using a block-aware instruction set
Energy, power, and area efficiency are critical design concerns for embedded processors. Much of the energy of a typical embedded processor is consumed in the front-end since inst...
Ahmad Zmily, Christos Kozyrakis
EUROPAR
2005
Springer
15 years 3 months ago
Improving Instruction Delivery with a Block-Aware ISA
Instruction delivery is a critical component for wide-issue processors since its bandwidth and accuracy place an upper limit on performance. The processor front-end accuracy and ba...
Ahmad Zmily, Earl Killian, Christos Kozyrakis
ICCD
2001
IEEE
120views Hardware» more  ICCD 2001»
15 years 6 months ago
Design of a Predictive Filter Cache for Energy Savings in High Performance Processor Architectures
Filter cache has been proposed as an energy saving architectural feature [9]. A filter cache is placed between the CPU and the instruction cache (I-cache) to provide the instruct...
Weiyu Tang, Rajesh K. Gupta, Alexandru Nicolau