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ICRA
1994
IEEE
118views Robotics» more  ICRA 1994»
15 years 1 months ago
Developing Parallel Architectures for Range and Image Sensors
We describe a cost-effective method for developing parallel architectures which increase the performance of range and image sensors. A parametrised edge detector and its systolic ...
Shaori Guo, Wayne Luk, Penelope Probert
DFT
2005
IEEE
110views VLSI» more  DFT 2005»
15 years 3 months ago
A design flow for protecting FPGA-based systems against single event upsets
SRAM-based Field Programmable Gate Arrays (FPGAs) are very susceptible to Single Event Upsets (SEUs) that may have dramatic effects on the circuits they implement. In this paper w...
Luca Sterpone, Massimo Violante
FPL
2005
Springer
86views Hardware» more  FPL 2005»
15 years 3 months ago
On the Reliability Evaluation of SRAM-Based FPGA Designs
Benefits of Field Programmable Gate Arrays (FPGAs) have lead to a spectrum of use ranging from consumer products to astronautics. This diversity necessitates the need to evaluate ...
Olivier Héron, Talal Arnaout, Hans-Joachim ...
BIOADIT
2004
Springer
15 years 3 months ago
A Hardware Implementation of a Network of Functional Spiking Neurons with Hebbian Learning
Abstract. In this paper we present a functional model of a spiking neuron intended for hardware implementation. Some features of biological spiking neuabstracted, while preserving ...
Andres Upegui, Carlos Andrés Peña-Re...
FPL
2004
Springer
87views Hardware» more  FPL 2004»
15 years 3 months ago
Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs
This paper presents an innovative way to deploy Bitstream Intellectual Property (BIP) cores. By using standard tools to generate bitstreams for Field Programmable Gate Arrays (FPGA...
Edson L. Horta, John W. Lockwood