Sciweavers

531 search results - page 15 / 107
» Field-Programmable Gate Arrays
Sort
View
IOLTS
2003
IEEE
124views Hardware» more  IOLTS 2003»
15 years 3 months ago
Designing FPGA based Self-Testing Checkers for m-out-of-n Codes
The paper describes a specific method for designing selfchecking checkers for m-out-of-n codes. The method is oriented to the Field Programmable Gate Arrays technology and is base...
A. Matrosova, Vladimir Ostrovsky, Ilya Levin, K. N...
IPPS
1999
IEEE
15 years 2 months ago
Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic
This paperpresents new resultson anapproach for solvingsatisfiability problems (SAT), that is, creating a logic circuit that is specialized to solve each problem instance on Field ...
Takayuki Suyama, Makoto Yokoo, Akira Nagoya
80
Voted
GLVLSI
1998
IEEE
129views VLSI» more  GLVLSI 1998»
15 years 1 months ago
Stochastic Evolution Algorithm For Technology Mapping
A new technology mapper SELF-Map for LookUp Table LUT based Field Programmable Gate Arrays FPGAs is described. SELF-Map is based on the Stochastic Evolution SE algorithm. The stat...
Ahmad S. Al-Mulhem, Alaaeldin Amin, Habib Youssef
87
Voted
IPPS
1998
IEEE
15 years 1 months ago
Implementing Parallelism in Random Discrete Event-Driven Simulation
Abstract. The inherently sequential nature of random discrete eventdriven simulation has made parallel and distributed processing di cult. This paper presents a method of applying ...
Marc Bumble, Lee D. Coraor
DFT
2007
IEEE
152views VLSI» more  DFT 2007»
15 years 1 months ago
TMR and Partial Dynamic Reconfiguration to mitigate SEU faults in FPGAs
This paper presents the adoption of the Triple Modular Redundancy coupled with the Partial Dynamic Reconfiguration of Field Programmable Gate Arrays to mitigate the effects of Sof...
Cristiana Bolchini, Antonio Miele, Marco D. Santam...