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ISMVL
1999
IEEE
76views Hardware» more  ISMVL 1999»
15 years 2 months ago
Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates
This paper considers an optimization method of programmable logic arrays (PLAs), which have two-input EXOR gate at the outputs. The PLA realizes an EXOR of two sum-of-products exp...
Debatosh Debnath, Tsutomu Sasao
ICS
1995
Tsinghua U.
15 years 1 months ago
Gated SSA-based Demand-Driven Symbolic Analysis for Parallelizing Compilers
In this paper, we present a GSA-based technique that performs more e cient and more precise symbolic analysis of predicated assignments, recurrences and index arrays. The e ciency...
Peng Tu, David A. Padua
EH
2003
IEEE
247views Hardware» more  EH 2003»
15 years 3 months ago
Evolvable Building Blocks for Analog Fuzzy Logic Controllers
This work discusses the use of an Evolvable Hardware (EHW) platform in the synthesis of analog electronic circuits for Fuzzy Logic Controllers. A Fuzzy Logic Controller (FLC) is d...
Jorge Luís Machado do Amaral, José F...
EH
2004
IEEE
115views Hardware» more  EH 2004»
15 years 1 months ago
Intrinsic Evolution of Digital-to-Analog Converters Using a CMOS FPTA Chip
The work presented here tackles the problem of designing a unipolar 6-bit digital-to-analog converter (DAC) with a voltage mode output by hardware evolution. Thereby a Field Progr...
Jörg Langeheine, Karlheinz Meier, Johannes Sc...
BIBE
2007
IEEE
150views Bioinformatics» more  BIBE 2007»
15 years 4 months ago
Differential Scoring for Systolic Sequence Alignment
Systolic implementations of dynamic programming solutions that utilize a similarity matrix can achieve appreciable performance with both course- and fine-grain parallelization. A ...
Antonio E. de la Serna