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ERSA
2006
70views Hardware» more  ERSA 2006»
14 years 11 months ago
Differential Reconfiguration Architecture suitable for a Holographic Memory
Optically Reconfigurable Gate Arrays (ORGAs), by exploiting the large storage capacity of holographic memory, offer the possibility of providing a virtual gate count that is much l...
Minoru Watanabe, Mototsugu Miyano, Fuminori Kobaya...
IPPS
1998
IEEE
15 years 2 months ago
A Parallel Algorithm for Minimum Cost Path Computation on Polymorphic Processor Array
This paper describes a new parallel algorithm for Minimum Cost Path computation on the Polymorphic Processor Array, a massively parallel architecture based on a reconfigurable mesh...
Pierpaolo Baglietto, Massimo Maresca, Mauro Miglia...
CODES
1994
IEEE
15 years 2 months ago
Towards a declarative framework for hardware-software codesign
We present an experimental framework for mapping declarative programs, written in a language known as Ruby, into various combinations of hardware and software. Strategies for para...
Wayne Luk, Teddy Wu
TITB
2008
117views more  TITB 2008»
14 years 9 months ago
Image-Based Gating of Intravascular Ultrasound Pullback Sequences
Intravascularultrasound (IVUS) sequences recorded in vivo are subject to a wide array of motion artifacts as the majority of these studies are performed within the coronary arterie...
Sean M. O'Malley, J. F. Granada, Stephane G. Carli...
ASPDAC
2009
ACM
137views Hardware» more  ASPDAC 2009»
15 years 1 months ago
Reconfigurable double gate carbon nanotube field effect transistor based nanoelectronic architecture
-- Carbon nanotubes (CNTs) and carbon nanotube field effect transistors (CNFETs) have demonstrated extraordinary properties and are widely accepted as the building blocks of next g...
Bao Liu