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IJCNN
2006
IEEE
15 years 3 months ago
A Scalable FPGA Implementation of Cellular Neural Networks for Gabor-type Filtering
— We describe an implementation of Gabor-type filters on field programmable gate arrays using the cellular neural network (CNN) architecture. The CNN template depends upon the ...
Ocean Y. H. Cheung, Philip Heng Wai Leong, Eric K....
DAC
2006
ACM
15 years 3 months ago
The zen of nonvolatile memories
Silicon technology based nonvolatile memories (NVM) have achieved widespread adoption for code and data storage applications. In the last 30 years, the traditional floating gate ...
Erwin J. Prinz
IPPS
2000
IEEE
15 years 2 months ago
Complexity Bounds for Lookup Table Implementation of Factored Forms in FPGA Technology Mapping
We consider technology mapping from factored form binary leaf-DAG to lookup tables LUTs, such as those found in eld programmable gate arrays. Polynomial time algorithms exist f...
Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi
SOCC
2008
IEEE
106views Education» more  SOCC 2008»
15 years 4 months ago
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control
First-in first-out (FIFO) memories are widely used in SoC for data buffering and flow control. In this paper, a robust ultra-low power asynchronous FIFO memory is proposed. With s...
Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
DATE
2007
IEEE
114views Hardware» more  DATE 2007»
15 years 4 months ago
Two-level microprocessor-accelerator partitioning
The integration of microprocessors and field-programmable gate array (FPGA) fabric on a single chip increases both the utility and necessity of tools that automatically move softw...
Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank V...