531 search results - page 84 / 107 » Field-Programmable Gate Arrays |
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...
ISQED
2009
IEEE
15 years 4 months ago
2009
IEEE
An outstanding challenge for realizing nanoelectronic systems is nano-interface design, i.e., how to precisely access a nanoscale wire in an array for communication between a nano...
IOLTS
2008
IEEE
15 years 4 months ago
2008
IEEE
— Error correcting coding is the dominant technique to achieve acceptable soft-error rates in memory arrays. In many modern circuits, the number of memory elements in the random ...
AHS
2006
IEEE
15 years 4 months ago
2006
IEEE
Traditional approaches to evolvable hardware (EHW), in which the field programmable gate array (FPGA) configuration is directly encoded, have not scaled well with increasing cir...
ARVLSI
1995
IEEE
15 years 1 months ago
1995
IEEE
This paper presents an architecture for generating a high-speed data pattern with precise edge placement resolution by using the matched delay technique. The technique involves ...