531 search results - page 86 / 107 » Field-Programmable Gate Arrays |
127
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ITNG
2007
IEEE
15 years 11 months ago
2007
IEEE
A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly couple...
118
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ISCAS
2006
IEEE
15 years 11 months ago
2006
IEEE
— Low-density parity-check convolutional codes offer the same good error-correcting performance as low-density parity-check block codes while having the ability to encode and dec...
135
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DATE
2005
IEEE
15 years 10 months ago
2005
IEEE
This paper explores methods for hardware acceleration of Hidden Markov Model (HMM) decoding for the detection of persons in still images. Our architecture exploits the inherent st...
123
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FPL
2005
Springer
15 years 10 months ago
2005
Springer
This work explores the effect of adding a timing driven functional decomposition step to the traditional field programmable gate array (FPGA) CAD flow. Once placement has comple...
148
Voted
ISLPED
2004
ACM
15 years 10 months ago
2004
ACM
In an attempt to enable the cost-effective production of lowand mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectur...