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DAC
2006
ACM
16 years 3 months ago
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, ...
ISCAS
2003
IEEE
97views Hardware» more  ISCAS 2003»
15 years 8 months ago
A multi-level static memory cell
This paper introduces a static multi-level memory cell that was conceived to store state variables in neuromorphic onchip learning applications. It consists of a capacitance that ...
Philipp Häfliger, Håvard Kolle Riis
ICDE
2010
IEEE
248views Database» more  ICDE 2010»
16 years 2 months ago
FPGA Acceleration for the Frequent Item Problem
Abstract-- Field-programmable gate arrays (FPGAs) can provide performance advantages with a lower resource consumption (e.g., energy) than conventional CPUs. In this paper, we show...
Gustavo Alonso, Jens Teubner, René Mül...
156
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GLVLSI
2009
IEEE
189views VLSI» more  GLVLSI 2009»
15 years 9 months ago
High-performance, cost-effective heterogeneous 3D FPGA architectures
In this paper, we propose novel architectural and design techniques for three-dimensional field-programmable gate arrays (3D FPGAs) with Through-Silicon Vias (TSVs). We develop a...
Roto Le, Sherief Reda, R. Iris Bahar
IPPS
1998
IEEE
15 years 7 months ago
Partial Rearrangements of Space-Shared FPGAs
Abstract Oliver Diessel1 and Hossam ElGindy2 1Department of Computer Science and Software Engineering 2Department of Electrical and Computer Engineering The University of Newcastle...
Oliver Diessel, Hossam A. ElGindy