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DATE
2005
IEEE
109views Hardware» more  DATE 2005»
15 years 9 months ago
Design Method for Constant Power Consumption of Differential Logic Circuits
Side channel attacks are a major security concern for smart cards and other embedded devices. They analyze the variations on the power consumption to find the secret key of the en...
Kris Tiri, Ingrid Verbauwhede
VTS
2005
IEEE
89views Hardware» more  VTS 2005»
15 years 9 months ago
Synthesis of Low Power CED Circuits Based on Parity Codes
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
Shalini Ghosh, Sugato Basu, Nur A. Touba
DATE
2010
IEEE
139views Hardware» more  DATE 2010»
15 years 8 months ago
Pareto efficient design for reconfigurable streaming applications on CPU/FPGAs
We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocate...
Jun Zhu, Ingo Sander, Axel Jantsch
APPROX
2006
Springer
106views Algorithms» more  APPROX 2006»
15 years 7 months ago
A Tight Lower Bound for the Steiner Point Removal Problem on Trees
Gupta (SODA'01) considered the Steiner Point Removal (SPR) problem on trees. Given an edge-weighted tree T and a subset S of vertices called terminals in the tree, find an edg...
Hubert T.-H. Chan, Donglin Xia, Goran Konjevod, An...
CSL
2006
Springer
15 years 7 months ago
Verification of Ptime Reducibility for System F Terms Via Dual Light Affine Logic
In a previous work we introduced Dual Light Affine Logic (DLAL) ([BT04]) as a variant of Light Linear Logic suitable for guaranteeing complexity properties on lambda-calculus terms...
Vincent Atassi, Patrick Baillot, Kazushige Terui