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FCCM
2007
IEEE
107views VLSI» more  FCCM 2007»
15 years 4 months ago
Optimizing Logarithmic Arithmetic on FPGAs
This paper proposes optimizations of the methods and parameters used in both mathematical approximation and hardware design for logarithmic number system (LNS) arithmetic. First, ...
Haohuan Fu, Oskar Mencer, Wayne Luk
ISCAS
2007
IEEE
167views Hardware» more  ISCAS 2007»
15 years 4 months ago
An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAM
— Reducing the leakage power in embedded SRAM memories is critical for low-power applications. Raising the source voltage of SRAM cells in standby mode reduces the leakage curren...
Afshin Nourivand, Chunyan Wang, M. Omair Ahmad
FCCM
2006
IEEE
144views VLSI» more  FCCM 2006»
15 years 4 months ago
Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA
In this paper, we investigate a combination of two techniques — instruction coding and instruction re-ordering — for optimizing energy in embedded processor control. We presen...
Robert G. Dimond, Oskar Mencer, Wayne Luk
SC
1995
ACM
15 years 1 months ago
Detecting Coarse - Grain Parallelism Using an Interprocedural Parallelizing Compiler
This paper presents an extensive empirical evaluation of an interprocedural parallelizing compiler, developed as part of the Stanford SUIF compiler system. The system incorporates...
Mary W. Hall, Saman P. Amarasinghe, Brian R. Murph...
APN
2005
Springer
15 years 2 days ago
Timed-Arc Petri Nets vs. Networks of Timed Automata
Abstract. We establish mutual translations between the classes of 1safe timed-arc Petri nets (and its extension with testing arcs) and networks of timed automata (and its subclass ...
Jirí Srba