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MICRO
2007
IEEE
141views Hardware» more  MICRO 2007»
14 years 15 days ago
Composable Lightweight Processors
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...
Changkyu Kim, Simha Sethumadhavan, M. S. Govindan,...
ICCAD
2001
IEEE
185views Hardware» more  ICCAD 2001»
14 years 3 months ago
Application-Driven Processor Design Exploration for Power-Performance Trade-off Analysis
1 - This paper presents an efficient design exploration environment for high-end core processors. The heart of the proposed design exploration framework is a two-level simulation e...
Diana Marculescu, Anoop Iyer
CASES
2006
ACM
13 years 10 months ago
Improving the performance and power efficiency of shared helpers in CMPs
Technology scaling trends have forced designers to consider alternatives to deeply pipelining aggressive cores with large amounts of performance accelerating hardware. One alterna...
Anahita Shayesteh, Glenn Reinman, Norman P. Jouppi...
SIGMETRICS
2012
ACM
251views Hardware» more  SIGMETRICS 2012»
11 years 8 months ago
Providing fairness on shared-memory multiprocessors via process scheduling
Competition for shared memory resources on multiprocessors is the most dominant cause for slowing down applications and makes their performance varies unpredictably. It exacerbate...
Di Xu, Chenggang Wu, Pen-Chung Yew, Jianjun Li, Zh...
HPCA
2009
IEEE
14 years 6 months ago
Adaptive Spill-Receive for robust high-performance caching in CMPs
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...
Moinuddin K. Qureshi