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92
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FPL
2000
Springer
124views Hardware» more  FPL 2000»
15 years 4 months ago
Balancing Logic Utilization and Area Efficiency in FPGAs
Abstract. In this paper we outline a procedure to determine appropriate partitioning of programmable logic and interconnect area to minimize overall device area across a broad rang...
Russell Tessier, Heather Giza
MA
2000
Springer
116views Communications» more  MA 2000»
15 years 4 months ago
Strong Mobility and Fine-Grained Resource Control in NOMADS
NOMADS is a Java-based agent system that supports strong mobility (i.e., the ability to capture and transfer the full execution state of migrating agents) and safe agent execution ...
Niranjan Suri, Jeffrey M. Bradshaw, Maggie R. Bree...
104
Voted
ICS
1995
Tsinghua U.
15 years 4 months ago
Optimum Modulo Schedules for Minimum Register Requirements
Modulo scheduling is an e cient technique for exploiting instruction level parallelism in a variety of loops, resulting in high performance code but increased register requirement...
Alexandre E. Eichenberger, Edward S. Davidson, San...
89
Voted
ISSS
1995
IEEE
109views Hardware» more  ISSS 1995»
15 years 4 months ago
1995 high level synthesis design repository
In this paper we brie y describe a set of designs that can serve as examples for High Level Synthesis (HLS) systems. The designs vary in complexity from simple behavioral nite st...
Preeti Ranjan Panda, Nikil D. Dutt
VL
1995
IEEE
158views Visual Languages» more  VL 1995»
15 years 4 months ago
DiaGen: A Generator for Diagram Editors Providing Direct Manipulation and Execution of Diagrams
Diagrams (e.g., flowcharts, trees for hierarchical structures, or graphs for finite state machines) are often needed as part of visual language systems and advanced user interfa...
Mark Minas, Gerhard Viehstaedt