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ICLP
2009
Springer
16 years 2 months ago
Preprocessing for Optimization of Probabilistic-Logic Models for Sequence Analysis
Abstract. A class of probabilistic-logic models is considered, which increases the expressibility from HMM's and SCFG's regular and contextfree languages to, in principle...
Henning Christiansen, Ole Torp Lassen
COMPSAC
2005
IEEE
15 years 7 months ago
An Empirical Performance Study for Validating a Performance Analysis Approach: PSIM
Performance analysis gains more attention in recent years by researchers who focus their study on the early software development stages to mitigate the risk of redesign as problem...
Jinchun Xia, Yujia Ge, Carl K. Chang
IEEEPACT
2006
IEEE
15 years 8 months ago
Testing implementations of transactional memory
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....
Chaiyasit Manovit, Sudheendra Hangal, Hassan Chafi...
DSD
2009
IEEE
152views Hardware» more  DSD 2009»
15 years 5 months ago
ARROW - A Generic Hardware Fault Injection Tool for NoCs
Todays NoCs are reaching a level where it is getting very hard to ensure 100% of functionality. Consequently, fault tolerance has become an important aspect in todays design techn...
Michael Birner, Thomas Handl
ECIS
2003
15 years 3 months ago
The method evaluation model: a theoretical model for validating information systems design methods
Information Systems (IS) design research tends to emphasise the development of new methods (normative research), while addressing the evaluation of methods in only a limited fashi...
Daniel L. Moody