4099 search results - page 274 / 820 » First Class Patterns |
143
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ICIP
2002
IEEE
16 years 8 months ago
2002
IEEE
In this paper, we present a novel PDE based error concealment algorithm. We formulate the error concealment problem as a sequential optimization problem with both smoothing and or...
146
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ICPR
2002
IEEE
16 years 7 months ago
2002
IEEE
Two years after the first edition, a new Fingerprint Verification Competition (FVC2002) was organized by the authors, with the aim of determining the state-of-theart in this chall...
138
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VLSID
2004
IEEE
16 years 6 months ago
2004
IEEE
Reduction of worst-case delay and delay uncertainty due to capacitive coupling is a still unsolved problem in physical design. We describe a routing only layout solution - swizzli...
141
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ICCAD
2006
IEEE
16 years 3 months ago
2006
IEEE
We devise a central triangular sequence to minimize the escape routing layers in area array packaging. We use a network flow model to analyze the bottleneck of the routable pins. ...
164
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DDECS
2008
IEEE
16 years 1 months ago
2008
IEEE
— Due to ever increasing design sizes more efficient tools for Automatic Test Pattern Generation (ATPG) are needed. Recently ATPG based on Boolean satisfiability (SAT) has been ...