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ICDCS
2012
IEEE
13 years 9 days ago
Combining Partial Redundancy and Checkpointing for HPC
Today’s largest High Performance Computing (HPC) systems exceed one Petaflops (1015 floating point operations per second) and exascale systems are projected within seven years...
James Elliott, Kishor Kharbas, David Fiala, Frank ...
ECSQARU
2009
Springer
15 years 4 months ago
Merging Belief Bases Represented by Logic Programs
Abstract. This paper presents a method which allows for merging beliefs expressed thanks to logic programming with stable model semantics. This method is based on the syntactic mer...
Julien Hué, Odile Papini, Eric Würbel
BIRTHDAY
2003
Springer
15 years 3 months ago
Digital Algebra and Circuits
Abstract. Digital numbers D are the world’s most popular data representation: nearly all texts, sounds and images are coded somewhere in time and space by binary sequences. The m...
Jean Vuillemin
IISWC
2008
IEEE
15 years 4 months ago
Accelerating multi-core processor design space evaluation using automatic multi-threaded workload synthesis
The design and evaluation of microprocessor architectures is a difficult and time-consuming task. Although small, handcoded microbenchmarks can be used to accelerate performance e...
Clay Hughes, Tao Li
IEEEPACT
2005
IEEE
15 years 3 months ago
HUNTing the Overlap
Hiding communication latency is an important optimization for parallel programs. Programmers or compilers achieve this by using non-blocking communication primitives and overlappi...
Costin Iancu, Parry Husbands, Paul Hargrove