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ASPDAC
1999
ACM
98views Hardware» more  ASPDAC 1999»
15 years 2 months ago
A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler
− In this paper, we propose a scheduling method for synchronous communication between threads in the Bach hardware compiler. In this method, all communications are extracted from...
Ryoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihi...
ICCAD
1994
IEEE
137views Hardware» more  ICCAD 1994»
15 years 1 months ago
Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints
We present in this paper a novel control synthesis technique for system-level specifications that are better described as a set of concurrent synchronous descriptions, their synch...
Claudionor José Nunes Coelho Jr., Giovanni ...
ACSD
2010
IEEE
215views Hardware» more  ACSD 2010»
14 years 7 months ago
A Formal Semantics of Clock Refinement in Imperative Synchronous Languages
The synchronous model of computation divides the execution of a program into an infinite sequence of socalled macro steps, which are further divided into finitely many micro steps....
Mike Gemunde, Jens Brandt, Klaus Schneider
MEMOCODE
2010
IEEE
14 years 7 months ago
Modular verification of synchronization with reentrant locks
We present a modular approach for verification of synchronization behavior in concurrent programs that use reentrant locks. Our approach decouples the verification of the lock impl...
Tevfik Bultan, Fang Yu, Aysu Betin-Can
IWNAS
2006
IEEE
15 years 3 months ago
A Fast Read/Write Process to Reduce RDMA Communication Latency
RDMA reduces network latency by eliminating unnecessary copies from network interface cards to application buffers, but how to reduce memory registration cost is a challenge. Prev...
Li Ou, Jizhong Han