107 search results - page 21 / 22 » Fixed-Polynomial Size Circuit Bounds |
CSL
2010
Springer
13 years 6 months ago
2010
Springer
We study probabilistic complexity classes and questions of derandomisation from a logical point of view. For each logic L we introduce a new logic BPL, bounded error probabilistic ...
TCC
2009
Springer
14 years 7 months ago
2009
Springer
We study the complexity of securely evaluating arithmetic circuits over finite rings. This question is motivated by natural secure computation tasks. Focusing mainly on the case o...
STACS
2010
Springer
14 years 1 months ago
2010
Springer
Kabanets and Impagliazzo [KI04] show how to decide the circuit polynomial identity testing problem (CPIT) in deterministic subexponential time, assuming hardness of some explicit ...
ISPD
2009
ACM
14 years 1 months ago
2009
ACM
As VLSI technology moves to the 65nm node and beyond, interconnect delay greatly limits the circuit performance. As a critical component in interconnect synthesis, layer assignmen...
ICCAD
2006
IEEE
14 years 3 months ago
2006
IEEE
With the advent of deep sub-micron (DSM) era, floorplanning has become increasingly important in physical design process. In this paper we clarify a misunderstanding in using Lag...