Sciweavers

134 search results - page 7 / 27
» Flexible Control of Data Transfers between Parallel Programs
Sort
View
MICRO
2006
IEEE
191views Hardware» more  MICRO 2006»
14 years 9 months ago
CAPSULE: Hardware-Assisted Parallel Execution of Component-Based Programs
Since processor performance scalability will now mostly be achieved through thread-level parallelism, there is a strong incentive to parallelize a broad range of applications, inc...
Pierre Palatin, Yves Lhuillier, Olivier Temam
GPC
2009
Springer
14 years 7 months ago
Application Level Interoperability between Clouds and Grids
SAGA is a high-level programming interface which provides the ability to develop distributed applications in an infrastructure independent way. In an earlier paper, we discussed ho...
André Merzky, Katerina Stamou, Shantenu Jha
APLAS
2008
ACM
14 years 11 months ago
Minimal Ownership for Active Objects
Active objects offer a structured approach to concurrency, encapsulating both unshared state and a thread of control. For efficient data transfer, data should be passed by referenc...
Dave Clarke, Tobias Wrigstad, Johan Östlund, ...
WMPI
2004
ACM
15 years 2 months ago
SCIMA-SMP: on-chip memory processor architecture for SMP
Abstract. In this paper, we propose a processor architecture with programmable on-chip memory for a high-performance SMP (symmetric multi-processor) node named SCIMA-SMP (Software ...
Chikafumi Takahashi, Masaaki Kondo, Taisuke Boku, ...
ISPA
2007
Springer
15 years 3 months ago
Parallelization Strategies for the Points of Interests Algorithm on the Cell Processor
The Cell processor is a typical example of a heterogeneous multiprocessor-on-chip architecture that uses several levels of parallelism to deliver high performance. Closing the gap ...
Tarik Saidani, Lionel Lacassagne, Samir Bouaziz, T...