1563 search results - page 101 / 313 » Flexible instruction processors |
96
Voted
APCSAC
2001
IEEE
15 years 4 months ago
2001
IEEE
During processor design, it is often necessary to evaluate multiple cache configurations. This paper describes the design and implementation of a retargetable on-line cache simula...
119
Voted
ASPDAC
2000
ACM
15 years 4 months ago
2000
ACM
The paper presents an application specific Java processor including reconfigurabilities, which is a DLX like pipeline processor with 5 stages and executes Java byte codes directly....
145
click to vote
ISPASS
2005
IEEE
15 years 6 months ago
2005
IEEE
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
117
Voted
DATE
2000
IEEE
15 years 5 months ago
2000
IEEE
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
119
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EURODAC
1994
IEEE
15 years 4 months ago
1994
IEEE
We outline a general methodology for the formal verification of pipeline conflicts in RISC cores. The different kinds of conflicts that can occur due to the simultaneous execution...