1563 search results - page 103 / 313 » Flexible instruction processors |
109
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ASPLOS
2004
ACM
15 years 6 months ago
2004
ACM
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Our sensor network asynchronous processor (SNAP/LE) is based on...
109
Voted
CASES
2006
ACM
15 years 6 months ago
2006
ACM
The architectural design of embedded systems is becoming increasingly idiosyncratic to meet varying constraints regarding energy consumption, code size, and execution time. Tradit...
124
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IPPS
2006
IEEE
15 years 6 months ago
2006
IEEE
Modern network processors support high levels of parallelism in packet processing by supporting multiple threads that execute on a micro-engine. Threads switch context upon encoun...
100
Voted
CF
2004
ACM
15 years 6 months ago
2004
ACM
Current instruction fetch policies in SMT processors are oriented towards optimization of overall throughput and/or fairness. However, they provide no control over how individual ...
112
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CF
2005
ACM
15 years 2 months ago
2005
ACM
In modern superscalar processors, the complex instruction scheduler could form the critical path of the pipeline stages and limit the clock cycle time. In addition, complex schedu...